package fpga_generation.java_base;
import java.util.*;

public class base_mm_master extends base_component
{
	private base_interface_mm master_port;
	public int bitwidth;
	private String interfaceName;
	
	ArrayList<Integer> addresses;
	ArrayList<base_mm_slave> connectedSlaves;
	
	public base_mm_master(String name, String interfaceName, int bitwidth)
	{
		super(name);
		this.interfaceName = interfaceName;
		this.bitwidth = bitwidth;
		addresses = new ArrayList<Integer>();
		connectedSlaves = new ArrayList<base_mm_slave>();
	}
	
	public void connect(base_mm_slave s, int address)
	{
		s.connect(this);
		addresses.add(address);
		connectedSlaves.add(s);
	}
	
	public String getInterface()
	{
		return name + "." + interfaceName;
	}
	
	public String writeRepr(int impl, int round)
	{	
		String output = "";
		if (round == 2) {
			for (int i=0; i<addresses.size(); i++) {
				String conString = getInterface() + "/" + connectedSlaves.get(i).getInterface();
				output += "add_connection " + conString + "\n";
			}
		}
		if (round == 3) {
			for (int i=0; i<addresses.size(); i++) {
				String conString = getInterface() + "/" + connectedSlaves.get(i).getInterface();
				output += "set_parameter " + conString + " arbitrationPriority \"1\"\n";
				output += "set_parameter " + conString + " baseAddress \"" + addresses.get(i) + "\"\n";
			}
		}
		return output;
	}
	
}